/******************************************************************************
 ** File Name:      pmu.c                                             *
 ** Author:         Chris                                              *
 ** DATE:           04/11/2014                                                *
 ** Copyright:      2014 Spreatrum, Incoporated. All Rights Reserved.         *
 ** Description:    This file defines the basic information on chip.          *
 ******************************************************************************

 ******************************************************************************
 **                        Edit History                                       *
 ** ------------------------------------------------------------------------- *
 ** DATE           NAME             DESCRIPTION                               *
 ** 04/11/2014     Chris               Create.                                   *
 ******************************************************************************/

/**---------------------------------------------------------------------------*
 **                         Dependencies                                      *
 **---------------------------------------------------------------------------*/
#include <asm/io.h>
#include "adi_hal_internal.h"
//#include "asm/arch/wdg_drvapi.h"
#include "asm/arch/sprd_reg.h"
#include "asm/arch-whale2/common.h"
/**---------------------------------------------------------------------------*
 **                         Compiler Flag                                     *
 **---------------------------------------------------------------------------*/
#ifdef   __cplusplus
extern   "C"
{
#endif

/**---------------------------------------------------------------------------*
 **                         Macro defines.
 **---------------------------------------------------------------------------*/
#define WHALE2_SRAM_REPAIR_EFUSE_BLOCK  3
#define WHALE2_SRAM_REPAIR_EFUSE_BIT1   27
#define WHALE2_SRAM_REPAIR_EFUSE_BIT2   19

/**---------------------------------------------------------------------------*
 **                         Struct defines.
 **---------------------------------------------------------------------------*/
/**---------------------------------------------------------------------------*
 **                         Global variables                                  *
 **---------------------------------------------------------------------------*/

/**---------------------------------------------------------------------------*
 **                         Function Definitions                              *
 **---------------------------------------------------------------------------*/
/**---------------------------------------------------------------------------*
 **                         Struct defines.
 **---------------------------------------------------------------------------*/
struct dcdc_core_ds_step_info{
	u32 ctl_reg;
	u32 ctl_sht;
	u32 cal_reg;
	u32 cal_sht;
};

#define CONFIG_PMU_CLK_4M
#define CONFIG_PMU_CLK_RC_4M
#define VDDARM_NOT_PD_IN_IDLE
#ifndef CONFIG_FPGA
void pmu_commom_config(void)
{
	uint32_t reg_val;
	#ifdef CONFIG_PMU_CLK_4M
	#ifdef CONFIG_PMU_CLK_XTL_4M

	CHIP_REG_SET(REG_PMU_APB_CGM_PMU_SEL,
		BIT_PMU_APB_AON_APB_PROTECT_RC_SEL(0x02) |
		BIT_PMU_APB_AON_APB_PROTECT_EN |
		BIT_PMU_APB_CGM_PMU_26M_EN |
		BIT_PMU_APB_CGM_PMU_26M_SEL |
		BIT_PMU_APB_CGM_PMU_SEL(0x02) |
		0
	);
	#elif defined(CONFIG_PMU_CLK_RC_4M)
	//CRISTAL FOR ON after RF power down fail at first time.
	CHIP_REG_OR(REG_AON_APB_RC100M_CFG,
		BIT_AON_APB_RC100M_AUTO_GATE_EN
	);

	CHIP_REG_OR(REG_PMU_APB_RC_REL_CFG,
		BIT_PMU_APB_RC1_FORCE_ON |
		BIT_PMU_APB_RC1_CM3_SEL |
		BIT_PMU_APB_RC1_AGCP_SEL |
		BIT_PMU_APB_RC1_WTLCP_SEL |
		BIT_PMU_APB_RC1_PUBCP_SEL |
		BIT_PMU_APB_RC1_AP_SEL|
		0
	);

	//put PMU sel at the last
	CHIP_REG_SET(REG_PMU_APB_CGM_PMU_SEL,
		BIT_PMU_APB_AON_APB_PROTECT_RC_SEL(0x02) |
		BIT_PMU_APB_AON_APB_PROTECT_EN |
		BIT_PMU_APB_CGM_PMU_26M_EN |
		BIT_PMU_APB_CGM_PMU_26M_SEL |
		BIT_PMU_APB_CGM_PMU_SEL(0x01) |
		0
	);
	CHIP_REG_AND(REG_PMU_APB_PAD_OUT_ADIE_CTRL0,
		~BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_CM3_DEEP_SLEEP_MASK |
		0
	);
	#endif

#ifdef VDDARM_NOT_PD_IN_IDLE
	CHIP_REG_OR(REG_PMU_APB_PMU_DUMMY_REG, BIT_PMU_APB_PMU_DUMMY_REG(0x2));
#endif
	CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
		//BIT_PMU_APB_PD_AP_SYS_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_AP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AP_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_AP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_AP_SYS_ISO_ON_DLY(0x07) |
		0
	);
#ifdef VDDARM_NOT_PD_IN_IDLE
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_TOP_CFG,
		//BIT_PMU_APB_PD_CA53_TOP_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_TOP_PD_SEL |
		//BIT_PMU_APB_PD_CA53_TOP_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_TOP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_TOP_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_TOP_PWR_ON_SEQ_DLY(0x03) |
		BIT_PMU_APB_PD_CA53_TOP_ISO_ON_DLY(0x06) |
		0
	);

	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_MP4_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_MP4_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_MP4_PD_SEL |
		//BIT_PMU_APB_PD_CA53_LIT_MP4_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_LIT_MP4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_SEQ_DLY(0x05) |
		BIT_PMU_APB_PD_CA53_LIT_MP4_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C0_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C0_PD_SEL |
		BIT_PMU_APB_CA53_LIT_C0_WAKEUP_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C0_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_LIT_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_SEQ_DLY(0x1F) |
		BIT_PMU_APB_PD_CA53_LIT_C0_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C1_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C1_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C1_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_SEQ_DLY(0x1D) |
		BIT_PMU_APB_PD_CA53_LIT_C1_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C2_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C2_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C2_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C2_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_SEQ_DLY(0x1B) |
		BIT_PMU_APB_PD_CA53_LIT_C2_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C3_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C3_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C3_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C3_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_SEQ_DLY(0x19) |
		BIT_PMU_APB_PD_CA53_LIT_C3_ISO_ON_DLY(0x04) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_MP4_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_MP4_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_MP4_PD_SEL |
		BIT_PMU_APB_PD_CA53_BIG_MP4_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_MP4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_SEQ_DLY(0x13) |
		BIT_PMU_APB_PD_CA53_BIG_MP4_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C0_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C0_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C0_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C0_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_SEQ_DLY(0x2D) |
		BIT_PMU_APB_PD_CA53_BIG_C0_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C1_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C1_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C1_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_SEQ_DLY(0x2B) |
		BIT_PMU_APB_PD_CA53_BIG_C1_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C2_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C2_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C2_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C2_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_SEQ_DLY(0x29) |
		BIT_PMU_APB_PD_CA53_BIG_C2_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C3_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C3_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C3_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C3_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_SEQ_DLY(0x27) |
		BIT_PMU_APB_PD_CA53_BIG_C3_ISO_ON_DLY(0x04) |
		0
	);
#else
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_TOP_CFG,
		//BIT_PMU_APB_PD_CA53_TOP_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_TOP_PD_SEL |
		//BIT_PMU_APB_PD_CA53_TOP_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_TOP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_TOP_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_TOP_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_CA53_TOP_ISO_ON_DLY(0x06) |
		0
	);

	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_MP4_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_MP4_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_MP4_PD_SEL |
		//BIT_PMU_APB_PD_CA53_LIT_MP4_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_LIT_MP4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_DLY(0xED) |
		BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_SEQ_DLY(0x06) |
		BIT_PMU_APB_PD_CA53_LIT_MP4_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C0_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C0_PD_SEL |
		BIT_PMU_APB_CA53_LIT_C0_WAKEUP_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C0_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_LIT_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_SEQ_DLY(0xF1) |
		BIT_PMU_APB_PD_CA53_LIT_C0_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C1_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C1_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C1_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_SEQ_DLY(0xF0) |
		BIT_PMU_APB_PD_CA53_LIT_C1_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C2_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C2_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C2_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C2_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_SEQ_DLY(0xEF) |
		BIT_PMU_APB_PD_CA53_LIT_C2_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C3_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C3_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C3_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C3_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_SEQ_DLY(0xEE) |
		BIT_PMU_APB_PD_CA53_LIT_C3_ISO_ON_DLY(0x04) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_MP4_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_MP4_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_MP4_PD_SEL |
		BIT_PMU_APB_PD_CA53_BIG_MP4_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_MP4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_DLY(0xED) |
		BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_SEQ_DLY(0x0E) |
		BIT_PMU_APB_PD_CA53_BIG_MP4_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C0_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C0_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C0_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C0_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_SEQ_DLY(0xF5) |
		BIT_PMU_APB_PD_CA53_BIG_C0_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C1_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C1_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C1_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_SEQ_DLY(0xF4) |
		BIT_PMU_APB_PD_CA53_BIG_C1_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C2_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C2_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C2_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C2_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_SEQ_DLY(0xF3) |
		BIT_PMU_APB_PD_CA53_BIG_C2_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C3_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C3_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C3_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C3_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_SEQ_DLY(0xF2) |
		BIT_PMU_APB_PD_CA53_BIG_C3_ISO_ON_DLY(0x04) |
		0
	);
#endif
	CHIP_REG_SET(REG_PMU_APB_PD_VSP_SYS_CFG ,
		//BIT_PMU_APB_PD_VSP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_VSP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_VSP_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_VSP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_VSP_SYS_ISO_ON_DLY(0x07) |
		0
	);
	#if 0  //not need to configure,confirm with ASIC
	CHIP_REG_SET(REG_PMU_APB_PD_DBG_SYS_CFG ,
		//BIT_PMU_APB_PD_DBG_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_DBG_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_DBG_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_DBG_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_DBG_SYS_ISO_ON_DLY(0x07) |
		0
	);
	#endif
	CHIP_REG_SET(REG_PMU_APB_PD_CAM_SYS_CFG ,
		//BIT_PMU_APB_PD_CAM_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CAM_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CAM_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_CAM_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_CAM_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_DISP_SYS_CFG ,
		//BIT_PMU_APB_PD_DISP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_DISP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_DISP_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_DISP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_DISP_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG ,
		//BIT_PMU_APB_PD_GPU_TOP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_TOP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_TOP_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_GPU_TOP_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_TOP_ISO_ON_DLY(0x07) |
		0
	);
	#if 0   //GPU power domain is in GPU inside,PMU cannot control
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C0_CFG ,
		//BIT_PMU_APB_PD_GPU_C0_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C0_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_C0_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_C0_ISO_ON_DLY(0x06) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C1_CFG ,
		//BIT_PMU_APB_PD_GPU_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C1_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_C1_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_GPU_C1_ISO_ON_DLY(0x05) |
		0
	);
	#endif
	reg_val	= CHIP_REG_GET(REG_PMU_APB_PD_PUB0_SYS_CFG) & 0xff000000;
	CHIP_REG_SET(REG_PMU_APB_PD_PUB0_SYS_CFG,
		//BIT_PMU_APB_PD_PUB0_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PUB0_SYS_AUTO_SHUTDOWN_EN |
		reg_val |
		BIT_PMU_APB_PD_PUB0_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_PUB0_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_PUB0_SYS_ISO_ON_DLY(0x07) |
		0
	);
	reg_val	= CHIP_REG_GET(REG_PMU_APB_PD_PUB1_SYS_CFG) & 0xff000000;
	CHIP_REG_SET(REG_PMU_APB_PD_PUB1_SYS_CFG,
		//BIT_PMU_APB_PD_PUB1_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PUB1_SYS_AUTO_SHUTDOWN_EN |
		reg_val |
		BIT_PMU_APB_PD_PUB1_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_PUB1_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_PUB1_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_SYS_CFG,
		BIT_PMU_APB_PD_WTLCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_SYS_ISO_ON_DLY(0x0B) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_TGDSP_CFG,
		BIT_PMU_APB_PD_WTLCP_TGDSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_TGDSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_TGDSP_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_TGDSP_PWR_ON_SEQ_DLY(0x0B) |
		BIT_PMU_APB_PD_WTLCP_TGDSP_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LDSP_CFG,
		BIT_PMU_APB_PD_WTLCP_LDSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LDSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LDSP_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LDSP_PWR_ON_SEQ_DLY(0x0A) |
		BIT_PMU_APB_PD_WTLCP_LDSP_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_HU3GE_A_CFG,
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_HU3GE_A_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_PWR_ON_SEQ_DLY(0x08) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_ISO_ON_DLY(0x04) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_GSM_CFG,
		BIT_PMU_APB_PD_WTLCP_GSM_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_GSM_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_GSM_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_GSM_PWR_ON_SEQ_DLY(0x07) |
		BIT_PMU_APB_PD_WTLCP_GSM_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_TD_CFG,
		BIT_PMU_APB_PD_WTLCP_TD_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_TD_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_TD_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_TD_PWR_ON_SEQ_DLY(0x06) |
		BIT_PMU_APB_PD_WTLCP_TD_ISO_ON_DLY(0x06) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P1_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P1_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_P1_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_WTLCP_LTE_P1_ISO_ON_DLY(0x0A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P2_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P2_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_P2_PWR_ON_SEQ_DLY(0x03) |
		BIT_PMU_APB_PD_WTLCP_LTE_P2_ISO_ON_DLY(0x09) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AGCP_SYS_CFG,
		BIT_PMU_APB_PD_AGCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AGCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AGCP_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_AGCP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_AGCP_SYS_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AGCP_DSP_CFG,
		BIT_PMU_APB_PD_AGCP_DSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AGCP_DSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AGCP_DSP_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_AGCP_DSP_PWR_ON_SEQ_DLY(0x03) |
		BIT_PMU_APB_PD_AGCP_DSP_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AGCP_GSM_CFG,
		BIT_PMU_APB_PD_AGCP_GSM_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AGCP_GSM_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AGCP_GSM_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_AGCP_GSM_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_AGCP_GSM_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_PUBCP_SYS_CFG,
		BIT_PMU_APB_PD_PUBCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PUBCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_PUBCP_SYS_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_PUBCP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_PUBCP_SYS_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P3_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P3_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_P3_PWR_ON_SEQ_DLY(0x04) |
		BIT_PMU_APB_PD_WTLCP_LTE_P3_ISO_ON_DLY(0x08) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P4_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P4_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P4_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_P4_PWR_ON_SEQ_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_P4_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_HU3GE_B_CFG,
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_HU3GE_B_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_PWR_ON_SEQ_DLY(0x07) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_HARQRAM_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_PWR_ON_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_PWR_ON_SEQ_DLY(0x09) |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AON_SYS_CFG,
		//BIT_PMU_APB_AON_WAKEUP_POR |
		//BIT_PMU_APB_PD_AON_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AON_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AON_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_AON_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_AON_SYS_ISO_ON_DLY(0x01) |
		0
	);
	#if 0   //GPU power domain is in GPU inside,PMU cannot control
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C2_CFG,
		//BIT_PMU_APB_PD_GPU_C2_RST_N_MASK |
		//BIT_PMU_APB_PD_GPU_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C2_PWR_ON_DLY(1) |
		BIT_PMU_APB_PD_GPU_C2_PWR_ON_SEQ_DLY(1) |
		BIT_PMU_APB_PD_GPU_C2_ISO_ON_DLY(1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C3_CFG,
		//BIT_PMU_APB_PD_GPU_C3_RST_N_MASK |
		//BIT_PMU_APB_PD_GPU_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C3_PWR_ON_DLY(1) |
		BIT_PMU_APB_PD_GPU_C3_PWR_ON_SEQ_DLY(1) |
		BIT_PMU_APB_PD_GPU_C3_ISO_ON_DLY(1) |
		0
	);
	#endif
	CHIP_REG_SET(REG_PMU_APB_RC_WAIT_CNT,
		BIT_PMU_APB_RC0_WAIT_CNT(0x03) |
		BIT_PMU_APB_RC1_WAIT_CNT(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
		BIT_PMU_APB_XTL0_WAIT_CNT(0x2b) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
		BIT_PMU_APB_XTLBUF2_WAIT_CNT(0x02) |
		BIT_PMU_APB_XTLBUF1_WAIT_CNT(0x02) |
		BIT_PMU_APB_XTLBUF0_WAIT_CNT(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
		BIT_PMU_APB_DPLL1_WAIT_CNT(0x07) |
		BIT_PMU_APB_DPLL0_WAIT_CNT(0x07) |
		BIT_PMU_APB_MPLL1_WAIT_CNT(0x07) |
		BIT_PMU_APB_MPLL0_WAIT_CNT(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
		BIT_PMU_APB_LTEPLL1_WAIT_CNT(0x07) |
		BIT_PMU_APB_LTEPLL_WAIT_CNT(0x07) |
		BIT_PMU_APB_TWPLL_WAIT_CNT(0x07) |
		BIT_PMU_APB_LVDSDIS_PLL_WAIT_CNT(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT3,
		BIT_PMU_APB_CPPLL_WAIT_CNT(0x07) |
		BIT_PMU_APB_GPLL_WAIT_CNT(0x07) |
		BIT_PMU_APB_RPLL1_WAIT_CNT(0x07) |
		BIT_PMU_APB_RPLL0_WAIT_CNT(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG0,
		BIT_PMU_APB_PUBCP_PWR_WAIT_CNT(0x01) |
		BIT_PMU_APB_AGCP_PWR_WAIT_CNT(0x01) |
		BIT_PMU_APB_WTLCP_PWR_WAIT_CNT(0x01) |
		BIT_PMU_APB_AP_PWR_WAIT_CNT(0x09) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG1,
		BIT_PMU_APB_SLP_CTRL_CLK_DIV_CFG(0x7C) |
		BIT_PMU_APB_CM3_PWR_WAIT_CNT(0x0) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_ST_DEBUG_DLY0,
		BIT_PMU_APB_CGM_OFF_DLY(0x02) |
		BIT_PMU_APB_CGM_ON_DLY(0x02) |
		BIT_PMU_APB_ISO_OFF_DLY(0x02) |
		BIT_PMU_APB_RST_DEASSERT_DLY(0x02) |
		0
	);
//it shuold use MACRO VDDARM_NOT_PD_IN_IDLE to distinguish,but the value is same,so...
	CHIP_REG_SET(REG_PMU_APB_PWR_ST_DEBUG_DLY1,
		BIT_PMU_APB_SHUTDOWN_M_D_DLY(0x04) |
		BIT_PMU_APB_PWR_ST_CLK_DIV_CFG(0x07) |
		BIT_PMU_APB_RST_ASSERT_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WAIT_CNT1,
		BIT_PMU_APB_PUBCP_PWR_PD_WAIT_CNT(0x0E) |
		BIT_PMU_APB_AGCP_PWR_PD_WAIT_CNT(0x0E) |
		BIT_PMU_APB_WTLCP_PWR_PD_WAIT_CNT(0x0E) |
		BIT_PMU_APB_AP_PWR_PD_WAIT_CNT(0x0E) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WAIT_CNT2,
		BIT_PMU_APB_CM3_PWR_PD_WAIT_CNT(0x0E) |
		0
	);
#ifdef VDDARM_NOT_PD_IN_IDLE
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY,
		BIT_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY(0x0) |
		0
	);
#else
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY,
		BIT_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY(0xE1) |
		0
	);
#endif
	#else
	CHIP_REG_SET(REG_PMU_APB_CGM_PMU_SEL,
		BIT_PMU_APB_AON_APB_PROTECT_RC_SEL(0x02) |
		BIT_PMU_APB_AON_APB_PROTECT_EN |
		BIT_PMU_APB_CGM_PMU_26M_EN |
		BIT_PMU_APB_CGM_PMU_26M_SEL |
		BIT_PMU_APB_CGM_PMU_SEL(0x00) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
		//BIT_PMU_APB_PD_AP_SYS_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_AP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AP_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_AP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_AP_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_TOP_CFG,
		//BIT_PMU_APB_PD_CA53_TOP_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_TOP_PD_SEL |
		//BIT_PMU_APB_PD_CA53_TOP_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_TOP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_TOP_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_TOP_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_CA53_TOP_ISO_ON_DLY(0x06) |
		0
	);

	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_MP4_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_MP4_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_MP4_PD_SEL |
		//BIT_PMU_APB_PD_CA53_LIT_MP4_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_LIT_MP4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_DLY(0x0A) |
		BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_SEQ_DLY(0x06) |
		BIT_PMU_APB_PD_CA53_LIT_MP4_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C0_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C0_PD_SEL |
		BIT_PMU_APB_CA53_LIT_C0_WAKEUP_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C0_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_CA53_LIT_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_SEQ_DLY(0x0e) |
		BIT_PMU_APB_PD_CA53_LIT_C0_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C1_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C1_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C1_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_SEQ_DLY(0x0d) |
		BIT_PMU_APB_PD_CA53_LIT_C1_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C2_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C2_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C2_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C2_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_SEQ_DLY(0x0c) |
		BIT_PMU_APB_PD_CA53_LIT_C2_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_C3_CFG,
		//BIT_PMU_APB_PD_CA53_LIT_C3_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_LIT_C3_PD_SEL |
		//BIT_PMU_APB_CA53_LIT_C3_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_LIT_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_LIT_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_SEQ_DLY(0x0b) |
		BIT_PMU_APB_PD_CA53_LIT_C3_ISO_ON_DLY(0x04) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_MP4_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_MP4_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_MP4_PD_SEL |
		BIT_PMU_APB_PD_CA53_BIG_MP4_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_MP4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_DLY(0x13) |
		BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_SEQ_DLY(0x07) |
		BIT_PMU_APB_PD_CA53_BIG_MP4_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C0_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C0_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C0_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C0_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C0_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_SEQ_DLY(0x12) |
		BIT_PMU_APB_PD_CA53_BIG_C0_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C1_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C1_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C1_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C1_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_SEQ_DLY(0x11) |
		BIT_PMU_APB_PD_CA53_BIG_C1_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C2_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C2_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C2_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C2_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_SEQ_DLY(0x10) |
		BIT_PMU_APB_PD_CA53_BIG_C2_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_BIG_C3_CFG,
		//BIT_PMU_APB_PD_CA53_BIG_C3_DBG_SHUTDOWN_EN |
		//BIT_PMU_APB_PD_CA53_BIG_C3_PD_SEL |
		//BIT_PMU_APB_CA53_BIG_C3_WAKEUP_EN |
		BIT_PMU_APB_PD_CA53_BIG_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CA53_BIG_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_SEQ_DLY(0x0e) |
		BIT_PMU_APB_PD_CA53_BIG_C3_ISO_ON_DLY(0x04) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_VSP_SYS_CFG ,
		//BIT_PMU_APB_PD_VSP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_VSP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_VSP_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_VSP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_VSP_SYS_ISO_ON_DLY(0x07) |
		0
	);
	#if 0  //not need to configure,confirm with ASIC
	CHIP_REG_SET(REG_PMU_APB_PD_DBG_SYS_CFG ,
		//BIT_PMU_APB_PD_DBG_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_DBG_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_DBG_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_DBG_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_DBG_SYS_ISO_ON_DLY(0x07) |
		0
	);
	#endif
	CHIP_REG_SET(REG_PMU_APB_PD_CAM_SYS_CFG ,
		//BIT_PMU_APB_PD_CAM_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_CAM_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_CAM_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_CAM_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_CAM_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_DISP_SYS_CFG ,
		//BIT_PMU_APB_PD_DISP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_DISP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_DISP_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_DISP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_DISP_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG ,
		//BIT_PMU_APB_PD_GPU_TOP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_TOP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_TOP_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_TOP_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_TOP_ISO_ON_DLY(0x07) |
		0
	);
	#if 0   //GPU power domain is in GPU inside,PMU cannot control
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C0_CFG ,
		//BIT_PMU_APB_PD_GPU_C0_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C0_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C0_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_C0_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_C0_ISO_ON_DLY(0x06) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C1_CFG ,
		//BIT_PMU_APB_PD_GPU_C1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C1_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_GPU_C1_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_GPU_C1_ISO_ON_DLY(0x05) |
		0
	);
	#endif
	//pub0_val = CHIP_REG_GET(REG_PMU_APB_PD_PUB0_SYS_CFG) & 0xff000000;
	CHIP_REG_SET(REG_PMU_APB_PD_PUB0_SYS_CFG,
		//BIT_PMU_APB_PD_PUB0_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PUB0_SYS_AUTO_SHUTDOWN_EN |
		//pub0_val |
		BIT_PMU_APB_PD_PUB0_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_PUB0_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_PUB0_SYS_ISO_ON_DLY(0x07) |
		0
	);
	//pub1_val = CHIP_REG_GET(REG_PMU_APB_PD_PUB1_SYS_CFG) & 0xff000000;
	CHIP_REG_SET(REG_PMU_APB_PD_PUB1_SYS_CFG,
		//BIT_PMU_APB_PD_PUB1_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PUB1_SYS_AUTO_SHUTDOWN_EN |
		//pub1_val |
		BIT_PMU_APB_PD_PUB1_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_PUB1_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_PUB1_SYS_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_SYS_CFG,
		BIT_PMU_APB_PD_WTLCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_SYS_ISO_ON_DLY(0x0B) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_TGDSP_CFG,
		BIT_PMU_APB_PD_WTLCP_TGDSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_TGDSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_TGDSP_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_TGDSP_PWR_ON_SEQ_DLY(0x0B) |
		BIT_PMU_APB_PD_WTLCP_TGDSP_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LDSP_CFG,
		BIT_PMU_APB_PD_WTLCP_LDSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LDSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LDSP_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_LDSP_PWR_ON_SEQ_DLY(0x0A) |
		BIT_PMU_APB_PD_WTLCP_LDSP_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_HU3GE_A_CFG,
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_HU3GE_A_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_PWR_ON_SEQ_DLY(0x08) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_A_ISO_ON_DLY(0x04) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_GSM_CFG,
		BIT_PMU_APB_PD_WTLCP_GSM_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_GSM_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_GSM_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_GSM_PWR_ON_SEQ_DLY(0x07) |
		BIT_PMU_APB_PD_WTLCP_GSM_ISO_ON_DLY(0x05) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_TD_CFG,
		BIT_PMU_APB_PD_WTLCP_TD_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_TD_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_TD_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_TD_PWR_ON_SEQ_DLY(0x06) |
		BIT_PMU_APB_PD_WTLCP_TD_ISO_ON_DLY(0x06) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P1_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P1_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P1_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P1_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_LTE_P1_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_WTLCP_LTE_P1_ISO_ON_DLY(0x0A) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P2_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P2_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_LTE_P2_PWR_ON_SEQ_DLY(0x03) |
		BIT_PMU_APB_PD_WTLCP_LTE_P2_ISO_ON_DLY(0x09) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AGCP_SYS_CFG,
		BIT_PMU_APB_PD_AGCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AGCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AGCP_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_AGCP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_AGCP_SYS_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AGCP_DSP_CFG,
		BIT_PMU_APB_PD_AGCP_DSP_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AGCP_DSP_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AGCP_DSP_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_AGCP_DSP_PWR_ON_SEQ_DLY(0x03) |
		BIT_PMU_APB_PD_AGCP_DSP_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AGCP_GSM_CFG,
		BIT_PMU_APB_PD_AGCP_GSM_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AGCP_GSM_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AGCP_GSM_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_AGCP_GSM_PWR_ON_SEQ_DLY(0x02) |
		BIT_PMU_APB_PD_AGCP_GSM_ISO_ON_DLY(0x02) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_PUBCP_SYS_CFG,
		BIT_PMU_APB_PD_PUBCP_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_PUBCP_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_PUBCP_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_PUBCP_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_PUBCP_SYS_ISO_ON_DLY(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P3_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P3_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_LTE_P3_PWR_ON_SEQ_DLY(0x04) |
		BIT_PMU_APB_PD_WTLCP_LTE_P3_ISO_ON_DLY(0x08) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_P4_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_P4_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_LTE_P4_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_P4_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_LTE_P4_PWR_ON_SEQ_DLY(0x05) |
		BIT_PMU_APB_PD_WTLCP_LTE_P4_ISO_ON_DLY(0x07) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_HU3GE_B_CFG,
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_WTLCP_HU3GE_B_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_PWR_ON_SEQ_DLY(0x07) |
		BIT_PMU_APB_PD_WTLCP_HU3GE_B_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WTLCP_LTE_HARQRAM_CFG,
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_FORCE_SHUTDOWN |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_PWR_ON_SEQ_DLY(0x09) |
		BIT_PMU_APB_PD_WTLCP_LTE_HARQRAM_ISO_ON_DLY(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_AON_SYS_CFG,
		//BIT_PMU_APB_AON_WAKEUP_POR |
		//BIT_PMU_APB_PD_AON_SYS_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_AON_SYS_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_AON_SYS_PWR_ON_DLY(0x01) |
		BIT_PMU_APB_PD_AON_SYS_PWR_ON_SEQ_DLY(0x01) |
		BIT_PMU_APB_PD_AON_SYS_ISO_ON_DLY(0x01) |
		0
	);
	#if 0   //GPU power domain is in GPU inside,PMU cannot control
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C2_CFG,
		//BIT_PMU_APB_PD_GPU_C2_RST_N_MASK |
		//BIT_PMU_APB_PD_GPU_C2_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C2_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C2_PWR_ON_DLY(1) |
		BIT_PMU_APB_PD_GPU_C2_PWR_ON_SEQ_DLY(1) |
		BIT_PMU_APB_PD_GPU_C2_ISO_ON_DLY(1) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_GPU_C3_CFG,
		//BIT_PMU_APB_PD_GPU_C3_RST_N_MASK |
		//BIT_PMU_APB_PD_GPU_C3_FORCE_SHUTDOWN |
		//BIT_PMU_APB_PD_GPU_C3_AUTO_SHUTDOWN_EN |
		BIT_PMU_APB_PD_GPU_C3_PWR_ON_DLY(1) |
		BIT_PMU_APB_PD_GPU_C3_PWR_ON_SEQ_DLY(1) |
		BIT_PMU_APB_PD_GPU_C3_ISO_ON_DLY(1) |
		0
	);
	#endif
	CHIP_REG_SET(REG_PMU_APB_RC_WAIT_CNT,
		BIT_PMU_APB_RC0_WAIT_CNT(0x03) |
		BIT_PMU_APB_RC1_WAIT_CNT(0x03) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
		BIT_PMU_APB_XTL0_WAIT_CNT(0x46) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
		BIT_PMU_APB_XTLBUF2_WAIT_CNT(0x01) |
		BIT_PMU_APB_XTLBUF1_WAIT_CNT(0x01) |
		BIT_PMU_APB_XTLBUF0_WAIT_CNT(0x01) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
		BIT_PMU_APB_DPLL1_WAIT_CNT(0x08) |
		BIT_PMU_APB_DPLL0_WAIT_CNT(0x08) |
		BIT_PMU_APB_MPLL1_WAIT_CNT(0x08) |
		BIT_PMU_APB_MPLL0_WAIT_CNT(0x08) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
		BIT_PMU_APB_LTEPLL1_WAIT_CNT(0x08) |
		BIT_PMU_APB_LTEPLL_WAIT_CNT(0x08) |
		BIT_PMU_APB_TWPLL_WAIT_CNT(0x08) |
		BIT_PMU_APB_LVDSDIS_PLL_WAIT_CNT(0x08) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT3,
		BIT_PMU_APB_CPPLL_WAIT_CNT(0x08) |
		BIT_PMU_APB_GPLL_WAIT_CNT(0x08) |
		BIT_PMU_APB_RPLL1_WAIT_CNT(0x08) |
		BIT_PMU_APB_RPLL0_WAIT_CNT(0x08) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG0,
		BIT_PMU_APB_PUBCP_PWR_WAIT_CNT(0x01) |
		BIT_PMU_APB_AGCP_PWR_WAIT_CNT(0x01) |
		BIT_PMU_APB_WTLCP_PWR_WAIT_CNT(0x01) |
		BIT_PMU_APB_AP_PWR_WAIT_CNT(0x09) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG1,
		BIT_PMU_APB_SLP_CTRL_CLK_DIV_CFG(0x7C) |
		BIT_PMU_APB_CM3_PWR_WAIT_CNT(0x0) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_ST_DEBUG_DLY0,
		BIT_PMU_APB_CGM_OFF_DLY(0x00) |
		BIT_PMU_APB_CGM_ON_DLY(0x00) |
		BIT_PMU_APB_ISO_OFF_DLY(0x00) |
		BIT_PMU_APB_RST_DEASSERT_DLY(0x00) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PWR_ST_DEBUG_DLY1,
		BIT_PMU_APB_SHUTDOWN_M_D_DLY(0x00) |
		BIT_PMU_APB_PWR_ST_CLK_DIV_CFG(0x07) |
		BIT_PMU_APB_RST_ASSERT_DLY(0x00) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WAIT_CNT1,
		BIT_PMU_APB_PUBCP_PWR_PD_WAIT_CNT(0x01) |
		BIT_PMU_APB_AGCP_PWR_PD_WAIT_CNT(0x01) |
		BIT_PMU_APB_WTLCP_PWR_PD_WAIT_CNT(0x01) |
		BIT_PMU_APB_AP_PWR_PD_WAIT_CNT(0x09) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_WAIT_CNT2,
		BIT_PMU_APB_CM3_PWR_PD_WAIT_CNT(0x00) |
		0
	);
	CHIP_REG_SET(REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY,
		BIT_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY(0x7D) |
		0
	);
	#endif
}

static void setup_autopd_mode(void)
{
	/*enable the emc auto gate en*/
	CHIP_REG_SET(REG_AON_APB_EMC_AUTO_GATE_EN,
		BIT_AON_APB_PUBCP_AON_AUTO_GATE_EN |
		BIT_AON_APB_AGCP_AON_AUTO_GATE_EN |
		BIT_AON_APB_WTLCP_AON_AUTO_GATE_EN |
		BIT_AON_APB_AP_AON_AUTO_GATE_EN |
		BIT_AON_APB_PUB_AON_AUTO_GATE_EN |
		BIT_AON_APB_CAM_DMC_AUTO_GATE_EN |
		BIT_AON_APB_DISP_DMC_AUTO_GATE_EN |
		BIT_AON_APB_VSP_DMC_AUTO_GATE_EN |
		BIT_AON_APB_PUBCP_DMC_AUTO_GATE_EN |
		BIT_AON_APB_AGCP_DMC_AUTO_GATE_EN |
		BIT_AON_APB_WTLCP_DMC_AUTO_GATE_EN |
		BIT_AON_APB_AP_DMC_AUTO_GATE_EN |
		BIT_AON_APB_CA53_DMC_AUTO_GATE_EN |
		0
	);
}

static void dcdc_core_ds_config(uint32_t core_cal_para, uint32_t core_ctrl_para)
{
	/*Get the chip id for eco chip*/
	if(0x1 == CHIP_REG_GET(REG_AON_APB_AON_VER_ID))
		ANA_REG_SET(ANA_REG_GLB_DCDC_CORE_SLP_CTRL1,
			BITS_DCDC_CORE_CAL_DS_SW(core_cal_para)|
			BITS_DCDC_CORE_CTRL_DS_SW(core_ctrl_para)
		);
	else {
		ANA_REG_AND(ANA_REG_GLB_SLP_DCDC_PD_CTRL,
			~BIT_SLP_DCDCCORE_DROP_EN
		);

		ANA_REG_AND(ANA_REG_GLB_SLP_DCDC_LP_CTRL,
			~BIT_SLP_DCDCCORE_LP_EN
		);
	}
}

static void sram_repair()
{
	u32 data = sprd_ap_efuse_read(WHALE2_SRAM_REPAIR_EFUSE_BLOCK);
	u32 check_bit1 = (data >> WHALE2_SRAM_REPAIR_EFUSE_BIT1) & 0x1;
	u32 check_bit2 = (data >> WHALE2_SRAM_REPAIR_EFUSE_BIT2) & 0x1;

	if( !check_bit1 && !check_bit2 )
		return;

	CHIP_REG_AND(REG_PMU_APB_PD_AON_SYS_CFG, ~BIT_PMU_APB_AON_WAKEUP_POR); //disable aon repair
	CHIP_REG_OR(REG_AON_APB_SUB_SYS_DBG_SIG6, 0x1); //enable efuse buffer rst_n
	CHIP_REG_OR(REG_AON_APB_SUB_SYS_DBG_SIG6, 0x2); //enable efuse buffer start
	udelay(60);  //delay for 60us
	CHIP_REG_SET(REG_PMU_APB_BISR_BYP_CFG1, 0x0); //enable all power domain repair
	CHIP_REG_AND(REG_PMU_APB_BISR_BYP_CFG2, 0x0); //enable all power domain repair
}

void CSP_Init(uint32_t gen_para)
{
	uint32_t reg_val;
	//setup_autopd_mode();
	sram_repair();
	pmu_commom_config();
	dcdc_core_ds_config(0,3);
}

#endif
/**---------------------------------------------------------------------------*
 **                         Compiler Flag                                     *
 **---------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif


